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1 ? fn6009.2 ISL5761 10-bit, +3.3v, 130/ 210+msps, high speed d/a converter the ISL5761 is a 10-bit, 130/210+msps (mega samples per second), cmos, high speed, low power, d/a (digital to analog) converter, designed specifically for use in high performance communicati on systems such as base transceiver stations utilizing 2.5g or 3g cellular protocols. this device complements the isl5x61 family of high speed converters, which include 10, 12, and 14-bit devices. pinout ISL5761 top view features ? speed grades . . . . . . . . . . . . . . . . 130m and 210+msps low power . . . . . 103mw with 20ma output at 130msps adjustable full scale output current . . . . . 2ma to 20ma +3.3v power supply 3v lvcmos compatible inputs excellent spurious free dynamic range (71dbc to nyquist, f s = 130msps, f out = 10mhz) umts adjacent channel power = 65db at 19.2mhz edge/gsm sfdr = 83dbc at 11mhz in 20mhz window pin compatible, 3.3v, lower power replacement for the ad9750 and hi5760 applications cellular infrastructure - single or multi-carrier: is-136, is- 95, gsm, edge, cdma2000, wcdma, tds-cdma bwa infrastructure medical/test instrumentation wireless communication systems high resolution imaging systems arbitrary waveform generators ordering information part number temp. range ( o c) package pkg. no. clock speed ISL5761ib -40 to 85 28 ld soic m28.3 130mhz ISL5761ia -40 to 85 28 ld tssop m28.173 130mhz ISL5761/2ib -40 to 85 28 ld soic m28.3 210mhz ISL5761/2ia -40 to 85 28 ld tssop m28.173 210mhz ISL5761eval1 25 soic evaluation platform 210mhz 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d9 (msb) d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clk dcom nc av dd comp ioutb nc fsadj refio reflo sleep dv dd iouta acom dcom dcom dcom dcom data sheet november 2001 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001, all rights reserved
2 typical applications circuit functional block diagram d9 (1) d8 (2) d7 (3) d6 (4) d5 (5) d4 (6) d9 d8 d7 d6 d5 d4 dcom (26, 11-14) clk (28) (24) av dd (22) iouta (21) ioutb (18) fsadj (16) reflo ISL5761 dv dd (27) 0.1 f 10 f (20) acom 50 ? (15) sleep (17) refio 0.1 f 1.91k ? ferrite 10 h (23) comp 0.1 f + bead r set d3 d2 d1 d0 d3 (7) d2 (8) d1 (9) d0 (lsb) (10) 0.1 f 10 h + bead (25, 19) nc acom dcom 10 f +3.3v (v dd ) 50 ? (50 ? ) 1:1, z1:z2 one connection any 50 ? load represents upper voltage reference (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d9 clk d7 d8 5-bit decoder refio cascode current source switch matrix bias generation int/ext 36 36 31 msb segments 5 lsbs + comp iouta ioutb input latch reflo fsadj sleep ISL5761
3 pin descriptions pin no. pin name description 1-10 d9 (msb) through d0 (lsb) digital data bit 9, (most significant bit) throu gh digital data bit 0, (least significant bit). 15 sleep control pin for power-down mode. sleep mode is active high; connect to ground for normal mode. sleep pin has internal 20 a active pulldown current. 16 reflo connect to analog ground to enable internal 1.2v reference or connect to av dd to disable internal reference. 17 refio reference voltage input if internal reference is disabled. reference voltage output if internal reference is enabled. use 0. 1 f cap to ground when internal reference is enabled. 18 fsadj full scale current adjust. use a resistor to ground to adjust full scale output current. full scale output current = 32 x v fsadj /r set . 19, 25 nc no connect. these should be grounded, but can be left disconnected. 21 ioutb the complementary current output of the device. full scale output current is achieved when all input bits are set to binary 0. 22 iouta current output of the device. full scale output current is achieved when all input bits are set to binary 1. 23 comp connect 0.1 f capacitor to acom. 24 av dd analog supply (+3.0v to +3.6v). 20 acom connect to analog ground. 26, 11-14 dcom connect to digital ground. 27 dv dd digital supply (+3.0v to +3.6v). 28 clk clock input. ISL5761
4 absolute maximum ratings thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . . +3.6v analog supply voltage av dd to acom . . . . . . . . . . . . . . . . . . +3.6v grounds, acom to dcom. . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v digital input voltages (d9-d0, clk, sleep). . . . . . . . dv dd + 0.3v reference input voltage range . . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values parameter test conditions t a = -40 o c to 85 o c units min typ max system performance resolution 10 - - bits integral linearity error, inl ?best fit? straight line (note 7) -0.5 0.1 +0.5 lsb differential linearity error, dnl (note 7) -0.5 0.1 +0.5 lsb offset error, i os iouta (note 7) -0.006 +0.006 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/ o c full scale gain error, fse with ex ternal reference (notes 2, 7) -3 0.5 +3 % fsr with internal reference (notes 2, 7) -3 0.5 +3 % fsr full scale gain drift with external reference (note 7) - 50 - ppm fsr/ o c with internal reference (note 7) - 100 - ppm fsr/ o c full scale output current, i fs 2-20ma output voltage compliance range (note 3) -1.0 - 1.25 v dynamic characteristics maximum clock rate, f clk ISL5761/2ia, ISL5761/2ib 210 250 - mhz maximum clock rate, f clk ISL5761ia, ISL5761ib 130 150 - mhz output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance -10 - pf output noise ioutfs = 20ma - 50 - pa/ hz ioutfs = 2ma - 30 - pa/ hz ac characteristics (using figure 13 with r diff = 50 ? and r load = 50 ? , full scale output = -2.5dbm ) spurious free dynamic range, sfdr within a window f clk = 210msps, f out = 80.8mhz, 30mhz span (notes 4, 7) - 72 - dbc f clk = 210msps, f out = 40.4mhz, 30mhz span (notes 4, 7) - 75 - dbc f clk = 130msps, f out = 20.2mhz, 20mhz span (notes 4, 7) - 77 - dbc ISL5761
5 spurious free dynamic range, sfdr to nyquist (f clk /2) f clk = 210msps, f out = 80.8mhz (notes 4, 7) - 50 - dbc f clk = 210msps, f out = 40.4mhz (notes 4, 7, 9) - 58 - dbc f clk = 200msps, f out = 20.2mhz, t = 25 o c (notes 4, 7) 58 60 - dbc f clk = 200msps, f out = 20.2mhz, t = -40 o c to 85 o c (notes 4, 7) 56 - - dbc f clk = 130msps, f out = 50.5mhz (notes 4, 7) - 55 - dbc f clk = 130msps, f out = 40.4mhz (notes 4, 7) - 60 - dbc f clk = 130msps, f out = 20.2mhz (notes 4, 7) - 68 - dbc f clk = 130msps, f out = 10.1mhz (notes 4, 7) - 70 - dbc f clk = 130msps, f out = 5.05mhz, t = 25 o c (notes 4, 7) 68 75 - dbc f clk = 130msps, f out = 5.05mhz, t = -40 o c to 85 o c (notes 4, 7) 66 - - dbc f clk = 100msps, f out = 40.4mhz (notes 4, 7) - 58 - dbc f clk = 80msps, f out = 30.3mhz (notes 4, 7) - 61 - dbc f clk = 80msps, f out = 20.2mhz (notes 4, 7) - 67 - dbc f clk = 80msps, f out = 10.1mhz (notes 4, 7, 9) - 69 - dbc f clk = 80msps, f out = 5.05mhz (notes 4, 7) - 74 - dbc f clk = 50msps, f out = 20.2mhz (notes 4, 7) - 66 - dbc f clk = 50msps, f out = 10.1mhz (notes 4, 7) - 72 - dbc f clk = 50msps, f out = 5.05mhz (notes 4, 7) - 75 - dbc spurious free dynamic range, sfdr in a window with eight tones f clk = 210msps, f out = 28.3mhz to 45.2mhz, 2.1mhz spacing, 50mhz span (notes 4, 7, 9) -63 - dbc f clk = 130msps, f out =17.5mhz to 27.9mhz, 1.3mhz spacing, 35mhz span (notes 4, 7) -66 - dbc f clk = 80msps, f out = 10.8mhz to 17.2mhz, 811khz spacing, 15mhz span (notes 4, 7) -73 - dbc f clk = 50msps, f out = 6.7mhz to 10.8mhz, 490khz spacing, 10mhz span (notes 4, 7) -75 - dbc spurious free dynamic range, sfdr in a window with edge or gsm f clk = 78msps, f out = 11mhz, in a 20mhz window, rbw=30khz (notes 4, 7, 9) -83 - dbc adjacent channel power ratio, acpr with umts f clk = 76.8msps, f out = 19.2mhz, rbw=30khz (notes 4, 7, 9) - 65 - db voltage reference internal reference voltage, v fsadj pin 18 voltage with internal reference 1.2 1.23 1.3 v internal reference voltage drift - 40 - ppm/ o c internal reference output current sink/source capability reference is not intended to be ex ternally loaded (refio pin) - 0 - a reference input impedance -1 -m ? reference input multiplying bandwidth (note 7) - 1.0 - mhz digital inputs d9-d0, clk input logic high voltage with 3.3v supply, v ih (note 3) 2.3 3.3 - v input logic low voltage with 3.3v supply, v il (note 3) - 0 1.0 v sleep input current, i ih -25 - +25 a electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max ISL5761
6 input logic current, i ih, il -20 - +20 a clock input current, i ih, il -10 - +10 a digital input capacitance, c in -5 - pf timing characteristics data setup time, t su see figure 15 - 1.5 - ns data hold time, t hld see figure 15 - 1.5 - ns propagation delay time, t pd see figure 15 - 1 - clock cycles clk pulse width, t pw1 , t pw2 see figure 15 (note 3) 2 - - ns power supply characteristics av dd power supply (note 8) 2.7 3.3 3.6 v dv dd power supply (note 8) 2.7 3.3 3.6 v analog supply current (i avdd ) 3.3v, ioutfs = 20ma - 27.5 28.5 ma 3.3v, ioutfs = 2ma - 10 - ma digital supply current (i dvdd ) 3.3v (note 5) - 3.7 5 ma 3.3v (note 6) - 6.5 8 ma supply current (i avdd ) sleep mode 3.3v, ioutfs = don?t care - 1.5 - ma power dissipation 3.3v, ioutfs = 20ma (note 5) - 103 111 mw 3.3v, ioutfs = 20ma (note 6) - 110 120 mw 3.3v, ioutfs = 2ma (note 5) - 45 - mw power supply rejection single supply (note 7) -0.125 - +0.125 %fsr/v notes: 2. gain error measured as the error in the ratio betw een the full scale output current and the current through r set (typically 625 a). ideally the ratio should be 32. 3. parameter guaranteed by design or char acterization and not production tested. 4. spectral measurements made with different ial transformer coupled output and no external filtering. for multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 5. measured with the clock at 130msps and the output frequency at 5mhz. 6. measured with the clock at 200m sps and the output frequency at 20mhz. 7. see ?definition of specifications?. 8. recommended operation is from 3.0v to 3.6v. operation below 3.0v is possi ble with some degradation in spectral performance. r eduction in analog output current may be necessary to maintain spectral performance. 9. see typical performance plots. electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max ISL5761
7 typical performance (+3.3v supply, using figure 13 with r diff = 100 ? and r load = 50 ? ) figure 1. edge at 11mhz, 78msps clock (83+dbc @ ? f = +6mhz) figure 2. edge at 11mhz, 78msps clock (75dbc - nyquist, 6db pad) figure 3. gsm at 11mhz, 78msps clock (86+dbc @ ? f = +6mhz, 3db pad) figure 4. gsm at 11mhz, 78msps clock (78dbc - nyquist, 9db pad) figure 5. four edge carriers at 12.4-15.6mhz, 800khz spacing, 78msps (67dbc - 20mhz window) figure 6. four gsm carriers at 12.4-15.6mhz, 78msps (71dbc - 20mhz window, 6db pad) spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw ISL5761
8 figure 7. umts at 19.2mhz, 76.8msps (65db 1stacpr, 64db 2ndacpr) figure 8. one tone at 10.1mhz, 80msps clock (71dbc - nyquist, 6db pad) figure 9. one tone at 40.4mhz, 210msps clock (61dbc - nyquist, 6db pad) figure 10. eight tones (crest factor=8.9) at 37mhz, 210msps clock, 2.1mhz spacing (64dbc - nyquist) figure 11. two tones (cf=6) at 8.5mhz, 50msps clock, 500khz spacing (80dbc - 10mhz window, 6db pad) figure 12. four tones (cf=8.1) at 14mhz, 80msps clock, 800khz spacing (70dbc - nyquist, 6db pad) typical performance (+3.3v supply, using figure 13 with r diff = 100 ? and r load = 50 ? ) (continued) spectral mask umts tdd p>43dbm bts ISL5761
9 definition of specifications adjacent channel power ratio, acpr, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be 1 lsb. a dnl specification of 1 lsb or less guarantees monotonicity. edge, enhanced data for global evolution, a tdma standard for cellular applications which uses 200khz bw, 8- psk modulated carriers. full scale gain drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per o c. full scale gain error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through r set ). gsm, global system for mobile communication, a tdma standard for cellular applications which uses 200khz bw, gmsk modulated carriers. integral linearity error, inl, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. internal reference voltage drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm per o c. offset drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage at iouta through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per degree o c. offset error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of iouta through a known resistance. offset error is defined as the maximum deviation of the iouta output current from a value of 0ma. output voltage compliance range, is the voltage limit imposed on the output. the output impedance should be chosen such that the voltage developed does not violate the compliance range. power supply rejection, is measured using a single power supply. the nominal supply voltage is varied 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage re ference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the frequency is increased until the amplitude of the output waveform is 0.707 (-3db) of its original value. spurious free dynamic range, sfdr , is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. total harmonic distortion, thd, is the ratio of the rms value of the fundamental out put signal to the rms sum of the first five harmonic components. umts, universal mobile telecommunications system, a w-cdma standard for cellular applications which uses 3.84mhz modulated carriers. detailed description the ISL5761 is a 10-bit, current out, cmos, digital to analog converter. the maximum update rate is at least 210+msps and can be powered by a single power supply in the recommended range of +3.0v to +3.6v. operation with clock rates higher than 210msps is possible; please contact the factory for more information. it consumes less than 120mw of power when using a +3.3v supply, the maximum 20ma of output current, and the data switching at 210msps. the architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. in previous architectures that contained all binary we ighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. by greatly reducing the amount of current switching at these major transitions, the overall glitch of the converter is dramatica lly reduced, improving settling time, transient problems, and accuracy. digital inputs and termination the ISL5761 digital inputs are guaranteed to 3v lvcmos levels. the internal register is updated on the rising edge of the clock. to minimize reflecti ons, proper termination should be implemented. if the lines driving the clock and the digital inputs are long 50 ? lines, then 50 ? termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). these termination resistors are not likely needed as long as the digital waveform source is within a few inches of the dac. for pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50-200 ?) prior to the dac?s inputs in order to reduce the amount of noise. ISL5761
10 power supply separate digital and analog power supplies are recommended. the allowable supply range is +2.7v to +3.6v. the recommended supply range is +3.0 to 3.6v (nominally +3.3v) to maintain optimum sfdr. however, operation down to +2.7v is possible with some degradation in sfdr. reducing the analog output current can help the sfdr at +2.7v. the sfdr values stated in the table of specifications were obtained with a +3.3v supply. ground planes separate digital and analog ground planes should be used. all of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. the same is true for the analog components and the analog ground plane. noise reduction to minimize power supply noise, 0.1 f capacitors should be placed as close as possible to the converter?s power supply pins, av dd and dv dd . also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. voltag e reference the internal voltage reference of the device has a nominal value of +1.23v with a 40ppm/ o c drift coefficient over the full temperature range of the converter. it is recommended that a 0.1 f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin (16) selects the reference. the internal reference can be selected if pin 16 is tied low (ground). if an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into refio, pin 17. the full scale output current of the converter is a function of the voltage reference used and the value of r set . i out should be within the 2ma to 20ma range, though operation below 2ma is possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.2v (pin 18). if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set) x 32. if the full scale output current is set to 20ma by using the internal voltage reference (1.2v) and a 1.91k ? r set resistor, then the input coding to output current will resemble the following: analog output iouta and ioutb are complementary current outputs. the sum of the two currents is always equal to the full scale output current minus one lsb. if single ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unused output be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -1.0v to 1.25v. r out (the impedance loading each current output) should be chosen so that the desired output voltage is produ ced in conjunction with the output full scale current. if a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. the output voltage equation is: v out = i out x r out . the most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. the maximum recommended output current is 20ma. differential output iouta and ioutb can be used in a differential-to-single- ended arrangement to achieve better harmonic rejection. with r diff = 50 ? and r load =50 ? , the circuit in figure 13 will provide a 500mv (-2.5dbm) signal at the output of the transformer if the full scale output current of the dac is set to 20ma (used for the electrical s pecifications table). values of r diff = 100 ? and r load =50 ? were used for the typical performance curves. the center tap in figure 13 must be grounded. in the circuit in figure 14, the user is left with the option to ground or float the center tap. the dc voltage that will exist at either iouta or ioutb if the center tap is floating is iout dc x (r a //r b ) v because r diff is dc shorted by the transformer. if the center tap is grounded, the dc voltage is 0v. recommended values for the circuit in figure 14 are r a =r b =50 ? , r diff =100 ? , assuming r load =50 ? . the performance of figure 13 and figure 14 is basically the same, however leaving the center tap of figure 14 floating allows the circuit to find a more balanced virtual ground, theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations. table 1. input coding vs output current with internal reference and rset=1.91k ? input code (d9-d0) iouta (ma) ioutb (ma) 11111 11111 20 0 10000 00000 10 10 00000 00000 0 20 ISL5761
11 propagation delay the converter requires two clock rising edges for data to be represented at the output. ea ch rising edge of the clock captures the present data wo rd and outputs the previous data. the propagation delay is t herefore 1/clk, plus <2ns of processing. see figure 15. test service intersil offers customer-specific testing of converters with a service called testdrive. to submit a request, fill out the testdrive form. the form can be found by doing an ?entire site search? at www.intersil.com on the words ?dac testdrive?. or, send a request to the technical support center. figure 13. output loading for datasheet measurements pin 21 pin 22 r diff ISL5761 r load ioutb iouta v out = (2 x iouta x r eq )v l oad seen by the transformer r load represents the 1:1 r eq = 0.5 x (r load // r diff ) at each output figure 14. alternative output loading pin 21 pin 22 ISL5761 ioutb iouta v out = (2 x iouta x r eq )v r eq = 0.5 x (r load // r diff // r a ), where r a =r b at each output r load r diff r a r b load seen by the transformer r load represents the timing diagram figure 15. propagation delay, setup time, hold time and minimum pulse width diagram clk i out 50% t pw1 t pw2 t su t hld t su t su t pd t hld t hld d9-d0 w 0 w 1 w 2 w 3 output=w 0 output=w 1 t pd output=w -1 ISL5761
12 ISL5761 small outline plastic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93
3-13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL5761 thin shrink small outline plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ae, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gat e burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m28.173 28 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 6/98

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